| Please code the divider by 3 with Verilog(50% duty cycle).用Verilog设计一个3分频器，要求50%占空比。 |
编程题 |
中等 |
笔试真题
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| Please describe the digital P&R flow.请简述数字后端P&R流程。 |
问答题 |
中等 |
笔试真题问答题
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| Please use a MUX and INV to implement aXOR.如何用一个2选一的MUX和一个INV实现异或。 |
问答题 |
中等 |
经典问答问答题
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| What are recovery and removal times? |
问答题 |
中等 |
经典问答问答题
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| The clock cycle is T, the clock toregister output delay is Tco, setup and hold time of a register are Tsetup andThold, … |
问答题 |
中等 |
经典问答问答题
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| What's the difference between a LATCH anda DFF? |
问答题 |
中等 |
经典问答问答题
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| What is IR-drop, in which area will beeasy to have IR-drop problem ? |
问答题 |
中等 |
经典问答问答题
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| How do you synchronize an asynchronousinput? |
问答题 |
中等 |
经典问答问答题
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| Please draw the state machine transmissiondiagram of the array detection 10010，code with Verilogand build the testbench… |
编程题 |
中等 |
笔试真题
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| What are gate-level simulations? |
问答题 |
中等 |
经典问答问答题
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| Please constrain the timing of clock andinput signal in the waveform, both are input pins for a chip. 请对下图中的输入时钟和输入数据进行… |
问答题 |
中等 |
经典问答问答题
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| There is an X present in my gate-levelsimulation due to a timing violation. How do you identify the source of it andthe… |
问答题 |
中等 |
经典问答问答题
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| Please describe the ECO flow(includingpre-mask ECO and post-mask ECO).请描述ECO流程，包括pre-mask和post-mask ECO。 |
问答题 |
中等 |
经典问答问答题
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| What are various techniques to resolverouting congestion? |
问答题 |
中等 |
经典问答问答题
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| Please describe the rtl with INV, AND, OR andDFF. 请用与、或、非门和寄存器画出代码所描述的电路。 |
编程题 |
中等 |
笔试真题
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| What are the different sources of powerconsumption? |
问答题 |
中等 |
经典问答问答题
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| Two modules share one single port ram,please design an Arbiter with following requirements （按要求编写代码）： |
单选题 |
中等 |
笔试真题单选
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| Implement below RTL logic with DFF andNOR/NAND/INV cells（按要求编写代码）： |
编程题 |
中等 |
笔试真题
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